1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of individually and readily performing control of a variety of design margins and access time according to each semiconductor memory device to thereby improve a reliability and performance of the semiconductor memory device.
2. Description of the Prior Art
In a semiconductor memory device, there is always a possibility of process variation. Actually, according to process steps to allow the memory device to be operated, the process variation occurs within a predetermined error range for a target value, in which process variation is essential to determine a performance of the memory device. Therefore, in designing the memory device, design margins are to be considered to permit the memory device to be operated even in a worst condition.
Therefore, after the process variation and the design margins are considered in designing a device, a simulation is performed, and the uppermost metal layer option is laid out in order to easily verify and to adjust the process variation and the design margins according to the result of the simulation. That is, at a stage of a sample product, the design margins are evaluated by an internal probing. Then, a metal layer is corrected by an FIB(Focus Ion Beam) outfit to be re-evaluated, and finally is corrected.
With reference to FIG. 1, a conventional semiconductor memory device includes a sense amplifier enabling unit 1 for outputting a sense amplifier enable signal SN according to decoding an address regarding word line; delays 2 for delaying the sense amplifier enable signal SN for a predetermined time provided from the sense amplifier enabling unit 1 and outputting a delayed sense amplifier enable signal SN'; a bit line sense amplfier 3 being enabled by the delayed sense amplifier enable signal SN' provided from the delays 2 and amplifying a minute electric potential difference in a pair of bit lines BL and BL; and a memory cell 4 being connected to the pair of bit lines BL and BL and a word line WL.
The delays 2 includes a plurality of sequentially connected delays TD.sub.0 -TD.sub.n and metal switches for bypass disposed at both ends of each delay TD.sub.0 -TD.sub.n.
The memory cell 4 includes an NMOS transistor 401 having a gate connected to the word line WL and a source connected to the bit line BL, and a capacitor 402 for storing data one end of which is connected to a drain of the NMOS transistor 401 and the other end a power voltage is applied to. A plurality of memory cell constructed the same as in the above memory cell 4 are arranged in array in the semiconductor memory device.
An operation of the semiconductor memory device as constructed above will now be described with reference to FIG. 2.
When a row address strobe signal(not shown) provided from an external source of a semiconductor memory device becomes active, a row address(not shown) is decoded, so that a signal inputted to a word line WL of a plurality of word lines is transitted to a high level.
Then, the NMOS transistor 401 is turned on and the data stored at the capacitor 402 is loaded at the bit lines BL. That is, for instance, if the data stored at the capacitor 402 is `0`, the electric potential of the bit line(BL) which has been precharged by chargestmring between the capacitor 402 and the bit line BL is reduced as much as .DELTA.V.
The sense amplifier enabling unit 1 outputs a sense amplifier enable signal SN of high level to a delay element TD.sub.0 of the delay 2. The sense amplifier enabling signal SN is delayed by each delay element TD.sub.0 -TD.sub.n or is bypassed by each metal switch S.sub.0 -S.sub.n, by which a delayed sense amplifier enabling signal SN' is input to a bit line sense amplifier 30. Accordingly, the bit line sense amplifier 3 is enabled to amplifier a predetermined voltage .DELTA.V, and the electric potential between the bit line BL and the bit line BL becomes large, as shown in FIG. 2.
In this respect, the charge dispersion between the capacitor 204 and the bit line BL is differently made depending on positions of memory cells each of which is connected to the bit line BL by RC delay. Therefore, if a farthest memory cell from the bit line sense amplifier 3 is selected, a size of the predetermined voltage .DELTA.V becomes the worst.
The bit line sense amplifier 3 always has an offset in sense amplifier, the element for geometrical mismatch and mismatch in process. In spite of the offset, the size of the predetermined voltage .DELTA.V between a pair of the bit line BL and BL is to be sufficient for sensing a proper data. However, since there is no means for supplying the charge but the capacitor 402 and the bit line capacitor(not shown), the predetermined voltage .DELTA.V will be converged to a constant value rather than being continuously increased as time goes by.
Therefore, for the purpose of sensing the proper data, the delayed sense amplifier enable signal SN' is to be input to the bit line sense amplifier 3 enough late, however, in this case, a time margin between a signal Ysel(not shown) selecting the bit line and the sense amplifier enabling signal SN may be reduced while an access time of the row address strobe signal RAS is increased. In particular, if an input point of time of the delayed sense amplifier enable signal SN' would be determined by only a simulation, the input point of time is necessarily be enough prolonged, moreover, a time margin is additionally required for a reliable operation considering the process variation and a die variation.
Accordingly, in order to avoid such problems, after evaluation of the operation of the sample product of the semiconductor memory device, arbitrary metal switches of the metal switches S.sub.0 -S.sub.n disposed at both ends of the delay elements TD.sub.0 -TD.sub.n are turned on or off, so that the input point of time of the delayed sense amplifier enable signal SN' is adjusted and the adjusted input point of time is applied to a device for real product.
However, such conventional semiconductor memory device also has disadvantages in that, since a uniformly defined time margin is applied to every semiconductor memory device, the time margin is unnecessarily larger for a specific semiconductor memory device, resulting in delaying the access time. Also, the sample product is evaluated by using FIB outfit which is hard to work, only a few sample products can be evaluated. In addition, in order to apply data obtained from the evaluation to a new product, the metal layer should be corrected, which is dangerous and a developing period of a semiconductor memory device therefor is lengthened. Furthermore, even if a process at the stage of mass production is improved, the result of the evaluation can not be quickly adapted to a manufacturing process.